Some engineers consider the most difficult part of integrated circuit design to be the determination of timing relationships between individual circuit elements. As chip complexity increases, STA techniques are often used to verify designs. Some analysis tools, such as PrimeTime® STA tools (“PrimeTime” is a registered trademark of Synopsys, Inc.), can provide full-chip, gate-level static timing analyses in a semi-automated manner. However, the repetitive nature of various data entry tasks may result in an erroneous analysis result.
For example, entering all of the data comprising an initial static timing environment prior to running an automated analysis can be quite tedious. Multiple engineers working on the same project may not adhere to standardized guidelines. In addition, false path designations applied by engineers to certain inter-clock paths for one operational mode may turn out to be valid paths in another mode. Finally, it may be necessary to manually create multiple clock generation files to support the existence of multiple sources for individual generated clocks. Any errors introduced as a part of implementing these tasks can easily propagate to the final result. Thus, improved consistency in developing the initial static timing environment, as well as greater uniformity in defining false paths and sources of generated clocks may reduce the number of errors present in the final analysis result.